STM32F098RC datasheet(15/128 Pages) STMICROELECTRONICS

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STM32F098CC STM32F098RC STM32F098VC

Functional overview

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Stop mode

Stop mode achieves very low power consumption while retaining the content of SRAM

and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the

HSE crystal oscillators are disabled.

The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line

source can be one of the 16 external lines, RTC, I2C1 USART1, USART3, COMPx.

The CEC, USART1, USART2, USART3 and I2C1 peripherals can be configured to

enable the HSI RC oscillator so as to get clock for processing incoming data.

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

mode.

3.6

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example on

failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the application to configure the frequency of the AHB and the APB

domains. The maximum frequency of the AHB and the APB domains is 48 MHz.

Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL

input source. This oscillator can be automatically fine-trimmed by the means of the CRS

peripheral using the external synchronization.

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