STM8SPLNB1 datasheet(9/44 Pages) STMICROELECTRONICS

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STM8SPLNB1

STM8SPLNB1 operation

STM8SPLNB1 has 8 output pins which can work as 4 I2C master channels. Each I2C

channel can address 2 LNB devices (2 different I2C addresses: 0xC8 and 0xCA) - see

Table 2: SaTCRs implementation - ST7LNB1 compatible mode and Table 3: SaTCRs

implementation - incremental order mode for assignment of given SaTCR to given I2C bus

and address.

Assignment depends from I2C addressing mode EEPROM parameter - see Table 14:

STM8SPLNB1 EEPROM parameters. As a convention, SaTCR1 must be associated to the

BPF having the lowest center frequency of the application, SaTCR2 to the BPF having the

next higher center frequency and so on.

Table 2. SaTCRs implementation - ST7LNB1 compatible mode

SatCR

number

SaTCR(1)

1. Selection of ST7LNB1 compatible mode: pin MODE (see Table 1: STM8SPLNB1 pins description) must be

grounded and I2C addressing mode EEPROM parameter (see Table 14: STM8SPLNB1 EEPROM

parameters) must be set to 0. Otherwise (e.g. pin MODE is left open or I2C addressing mode EEPROM

parameter is set to 1) is used incremental order mode.

SaTCR address

I2C number

SaTCR1

0xC8

I2C1

SaTCR2

0xCA

SaTCR3

0xC8

I2C2

SaTCR4

0xCA

SaTCR5

0xC8

I2C3

SaTCR6

0xCA

SaTCR7

0xC8

I2C4

SaTCR8/ legacy SaTCR

(for wide RF band

applications)

0xCA

Table 3. SaTCRs implementation - incremental order mode

SatCR

number

SaTCR(1)

SaTCR address

I2C number

SaTCR1

0xC8

I2C1

SaTCR2

0xCA

I2C2

SaTCR3

0xC8

I2C3

SaTCR4

0xCA

I2C4

SaTCR5

0xCA

I2C1

SaTCR6

0xC8

I2C2

SaTCR7

0xCA

I2C3

SaTCR8/ legacy SaTCR (for

wide RF band applications)

0xC8

I2C4

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