ST72361AR4-Auto datasheet(207/279 Pages) STMICROELECTRONICS

207 / 279 page

ST72361xx-Auto

LINSCI serial communication interface (LIN master only)

Doc ID 12468 Rev 3

207/279

16.8.2

Control register 1 (SCICR1)

Read/ write

Reset value: x000 0000 (x0h)

Bit 7 = R8 Receive data bit 8.

This bit is used to store the 9th bit of the received word when M = 1.

Bit 6 = T8 Transmit data bit 8.

This bit is used to store the 9th bit of the transmitted word when M = 1.

Bit 5 = SCID Disabled for low power consumption

When this bit is set the SCI prescalers and outputs are stopped and the end of the current

byte transfer in order to reduce power consumption.This bit is set and cleared by software.

0: SCI enabled

1: SCI prescaler and outputs disabled

Bit 4 = M Word length.

This bit determines the word length. It is set or cleared by software.

0: 1 start bit, 8 data bits, 1 stop bit

1: 1 start bit, 9 data bits, 1 stop bit

Note:

The M bit must not be modified during a data transfer (both transmission and reception).

Bit 3 = WAKE Wake-Up method.

This bit determines the SCI Wake-Up method, it is set or cleared by software.

0: idle line

1: address mark

Bit 2 = PCE Parity control enable.

This bit selects the hardware parity control (generation and detection). When the parity

control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th

bit if M = 0) and parity is checked on the received data. This bit is set and cleared by

software. Once it is set, PCE is active after the current byte (in reception and in

transmission).

0: parity control disabled

1: parity control enabled

Bit 1 = PS Parity selection.

This bit selects the odd or even parity when the parity generation/detection is enabled (PCE

bit set). It is set and cleared by software. The parity is selected after the current byte.

0: even parity

1: odd parity

Bit 0 = PIE Parity interrupt enable.

This bit enables the interrupt capability of the hardware parity control when a parity error is

detected (PE bit set). It is set and cleared by software.

0: parity error interrupt disabled

1: parity error interrupt enabled

SCID

WAKE

PCE

PIE

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