ST72361AR4-Auto datasheet(173/279 Pages) STMICROELECTRONICS

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ST72361xx-Auto

LINSCI serial communication interface (LIN master/slave)

Doc ID 12468 Rev 3

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15.8.7

Extended transmit prescaler division register (SCIETPR)

Read/ write

Reset value: 0000 0000 (00h)

Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register.

The extended baud rate generator is activated when a value other than 00h is stored in this

factor set in the SCIETPR register (in the range 1 to 255).

The extended baud rate generator is not active after a reset.

Note:

In LIN slave mode, the conventional and extended baud rate generators are disabled.

15.9

LIN mode - functional description.

The block diagram of the Serial Control Interface, in LIN slave mode is shown in Figure 81.

It uses six registers:

●

3 control registers: SCICR1, SCICR2 and SCICR3

●

2 status registers: the SCISR register and the LHLR register mapped at the SCIERPR

address

●

A baud rate register: LPR mapped at the SCIBRR address and an associated fraction

The bits dedicated to LIN are located in the SCICR3. Refer to the register descriptions in

Section 15.10: LIN mode register descriptionfor the definitions of each bit.

15.9.1

Entering LIN mode

To use the LINSCI in LIN mode the following configuration must be set in SCICR3 register:

●

Clear the M bit to configure 8-bit word length.

●

Set the LINE bit.

Master

To enter master mode the LSLV bit must be reset In this case, setting the SBK bit will send

13 low bits.

Then the baud rate can programmed using the SCIBRR, SCIERPR and SCIETPR registers.

In LIN master mode, the conventional and/ or extended prescaler define the baud rate (as in

standard SCI mode)

Slave

Set the LSLV bit in the SCICR3 register to enter LIN slave mode. In this case, setting the

SBK bit will have no effect.

ETPR7

ETPR6

ETPR5

ETPR4

ETPR3

ETPR2

ETPR1

ETPR0

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