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ST72361AR4-Auto bảng dữ liệu(PDF) 172 Page - STMicroelectronics

tên linh kiện ST72361AR4-Auto
Giải thích chi tiết về linh kiện  Clock, reset and supply management
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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ST72361AR4-Auto bảng dữ liệu(HTML) 172 Page - STMicroelectronics

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LINSCI serial communication interface (LIN master/slave)
ST72361xx-Auto
172/279
Doc ID 12468 Rev 3
Bits 2:0 = SCR[2:0] SCI Receiver rate divider.
These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus
clock to yield the receive rate clock in conventional Baud Rate Generator mode.
15.8.6
Extended receive prescaler division register (SCIERPR)
Read/ write
Reset value: 0000 0000 (00h)
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Prescaler Register.
The extended baud rate generator is activated when a value other than 00h is stored in this
register. The clock frequency from the 16 divider (see Figure 79) is divided by the binary
factor set in the SCIERPR register (in the range 1 to 255).
The extended baud rate generator is not active after a reset.
16
1
0
0
32
1
64
1
0
128
1
Table 65.
Receiver rate divider
RR dividing factor
SCR2
SCR1
SCR0
1
0
0
0
21
4
1
0
81
16
1
0
0
32
1
64
1
0
128
1
Table 64.
Transmitter rate divider
TR dividing factor
SCT2
SCT1
SCT0
7
0
ERPR7
ERPR6
ERPR5
ERPR4
ERPR3
ERPR2
ERPR1
ERPR0



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