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STM8L101x2 bảng dữ liệu(PDF) 49 Page - STMicroelectronics

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STM8L101x1 STM8L101x2 STM8L101x3
Electrical parameters
63
Figure 20. Typical VIL and VIH vs. VDD (High sink I/Os)
Ilkg
Input leakage current (4)
VSS VIN VDD
Standard I/Os
-
-
50 (5)
nA
VSS VIN VDD
True open drain I/Os
-
-
200(5)
VSS VIN VDD
PA0 with high sink LED
driver capability
-
-
200(5)
RPU
Weak pull-up equivalent resistor(6)
VIN = VSS
30
45
60
k
Ω
CIO(7)
I/O pin capacitance
-
-
5
-
pF
1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.
2. Guaranteed by characterization results.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Not tested in production.
6. RPU pull-up equivalent resistor based on a resistive transistor (corresponding IPU current characteristics described in
Figure 22).
7. Guaranteed by design.
Table 26. I/O static characteristics (1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit



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