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ST72325AR9-Auto bảng dữ liệu(PDF) 79 Page - STMicroelectronics |
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ST72325AR9-Auto bảng dữ liệu(HTML) 79 Page - STMicroelectronics |
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79 / 243 page ![]() Obsolete Product(s) - Obsolete Product(s) ST72325xxx-Auto I/O ports Doc ID 13770 Rev 3 79/243 9.4 Low power modes 9.5 Interrupts The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction). Port B PB7, PB3 floating floating interrupt open-drain push-pull PB6:5, PB4, PB2:0 floating pull-up interrupt open-drain push-pull Port C PC7:0 floating pull-up open-drain push-pull Port D PD7:0 floating pull-up open-drain push-pull Port E PE7:3, PE1:0 floating pull-up open-drain push-pull PE2 pull-up open-drain(1) push-pull(1) Port F PF7:3 floating pull-up open-drain push-pull PF2 floating floating interrupt open-drain push-pull PF1:0 floating pull-up interrupt open-drain push-pull 1. Pull-up is always enabled leading to unwanted power consumption if output is tied to low level Table 32. I/O port configuration (continued) Port Pin name Input (DDR = 0) Output (DDR = 1) OR = 0 OR = 1 OR = 0 OR = 1 Table 33. Effect of low power modes on I/O ports Mode Effect Wait No effect on I/O ports. External interrupts cause the device to exit from Wait mode. Halt No effect on I/O ports. External interrupts cause the device to exit from Halt mode. Table 34. I/O port interrupt control/wake-up capability Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt External interrupt on selected external event - DDRx, ORx Yes Yes Table 35. I/O port register map and reset values Address (Hex.) Register label 76543210 Reset value of all I/O port registers 00000000 0000h PADR MSB LSB 0001h PADDR 0002h PAOR |
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