ST72345C4 datasheet(141/247 Pages) STMICROELECTRONICS

141 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

141/247

after the falling edge occurs, during the sampling of the 16 samples, if one of the

samples numbered 3, 5 or 7 is detected as a “1”.

–

During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is

detected as a “1”.

●

Therefore, a valid Start bit must satisfy both the above conditions to prevent the Noise

Flag getting set.

●

Data bits: the noise flag (NF) is set during normal data bit reception if the following

condition occurs:

–

During the sampling of 16 samples, if all three samples numbered 8, 9 and 10 are

not the same. The majority of the 8th, 9th and 10th samples is considered as the

bit value.

Therefore, a valid Data bit must have samples 8, 9 and 10 at the same value to prevent the

Noise Flag getting set.

Figure 66.

Bit sampling in reception mode

11.5.5

Low-power modes

RDI LINE

Sample

clock

12345678910

11 12

sampled values

One bit time

6/16

7/16

Table 57.

Mode description

Mode

Description

Wait

No effect on SCI.

SCI interrupts cause the device to exit from Wait mode.

Halt

SCI registers are frozen.

In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

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