ST72325AR7-Auto datasheet(210/243 Pages) STMICROELECTRONICS

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Electrical characteristics

ST72325xxx-Auto

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Doc ID 13770 Rev 3

19.9

Control pin characteristics

19.9.1

Asynchronous RESET pin

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Table 130.

Asynchronous RESET pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage(1)

0.3xVDD

VIH

Input high level voltage(1)

0.7xVDD

Vhys

Schmitt trigger voltage

hysteresis(2)

2.5

VOL

Output low level voltage(3)

VDD =5V, IIO = +2mA

0.2

0.5

IIO

Input current on RESET pin

RON

Weak pull-up equivalent resistor

120



tw(RSTL)out Generated reset pulse duration

Stretch applied on external pulse

42(4)

µs

Internal reset sources

42(4)

th(RSTL)in External reset pulse hold time

(5)

2.5

tg(RSTL)in Filtered glitch duration

(6)

200

Data based on characterization results, not tested in production.

Hysteresis voltage between Schmitt trigger switching levels.

The IIO current sunk must always respect the absolute maximum rating specified in Section 19.2.2 and the sum of IIO (I/O

ports and control pins) must not exceed IVSS.

Data guaranteed by design, not tested in production.

To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the

RESET pin with a duration below th(RSTL)in can be ignored.

The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy

environments.

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