ST72325AR7-Auto datasheet(198/243 Pages) STMICROELECTRONICS

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ST72325xxx-Auto

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Doc ID 13770 Rev 3

19.5

Clock and timing characteristics

Subject to general operating conditions for VDD, fCPU, and TA.

19.5.1

General timings

19.5.2

External clock source

Figure 76.

Typical application with an external clock source

Table 115.

General timings

Symbol

Parameter

Conditions

Min

Typ(1)

Data based on typical application software.

Max

Unit

tc(INST) Instruction cycle time

tCPU

fCPU = 8 MHz

250

375

1500

tv(IT)

Interrupt reaction time(2)

tv(IT) = tc(INST) + 10

Time measured between interrupt event and interrupt vector fetch.

t

c(INST) is the number of tCPU cycles

needed to finish the current instruction execution.

tCPU

fCPU =8MHz

1.25

2.75

µs

Table 116.

External clock source

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VOSC1H

OSC1 input pin high level voltage

See Figure 76

0.7xVDD

VDD

VOSC1L

OSC1 input pin low level voltage

VSS

0.3xVDD

tw(OSC1H)

tw(OSC1L)

OSC1 high or low time(1)

Data based on design simulation and/or technology characteristics, not tested in production.

tr(OSC1)

tf(OSC1)

OSC1 rise or fall time(1)

Ilkg

OSC1 input leakage current

VSS < VIN < VDD

±1

µA

OSC1

OSC2

fOSC

EXTERNAL

ST72XXX

CLOCK SOURCE

Not connected internally

VOSC1L

VOSC1H

tr(OSC1)

tf(OSC1)

tw(OSC1H)

tw(OSC1L)

Ilkg

90%

10%

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