ST72325AR7-Auto datasheet(151/243 Pages) STMICROELECTRONICS

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ST72325xxx-Auto

Serial communications interface (SCI)

Doc ID 13770 Rev 3

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15.7

SCI registers

15.7.1

Status register (SCISR)

Idle Line Detected

IDLE

ILIE

Yes

Parity Error

PIE

Yes

Table 73.

SCI interrupt control/wake-up capability

Interrupt event

Event flag

Enable control

bit

Exit from

Wait

Exit from

Halt

SCISR

Reset value: 1100 0000 (C0h)

543

TDRE

RDRF

IDLE

Table 74.

SCISR register description

Bit

Name

Function

7TDRE

Transmit data register empty

This bit is set by hardware when the content of the TDR register has been

transferred into the shift register. An interrupt is generated if the TIE bit = 1 in the

SCICR2 register. It is cleared by a software sequence (an access to the SCISR

0: Data is not transferred to the shift register

1: Data is transferred to the shift register

Note: Data is not transferred to the shift register unless the TDRE bit is cleared.

6TC

Transmission complete

This bit is set by hardware when transmission of a frame containing Data is

complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared

by a software sequence (an access to the SCISR register followed by a write to the

SCIDR register).

0: Transmission is not complete

1: Transmission is complete

Note: TC is not set after the transmission of a Preamble or a Break.

RDRF

Received data ready flag

This bit is set by hardware when the content of the RDR register has been

transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2

followed by a read to the SCIDR register).

0: Data is not received

1: Received data is ready to be read

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