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Serial peripheral interface (SPI)

ST72325xxx-Auto

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Doc ID 13770 Rev 3

14.8.2

Control/status register (SPICSR)

1:0

SPR[1:0]

Serial Clock Frequency

These bits are set and cleared by software. Used with the SPR2 bit, they select

the baud rate of the SPI serial clock SCK output by the SPI in master mode.

Note: These 2 bits have no effect in slave mode.

Table 68.

SPI master mode SCK frequency

Serial clock

SPR2

SPR1

SPR0

fCPU/4

100

fCPU/8

000

fCPU/16

001

fCPU/32

110

fCPU/64

010

fCPU/128

011

Table 67.

SPICR register description (continued)

Bit

Name

Function

SPICSR

Reset value: 0000 0000 (00h)

543

SPIF

WCOL

OVR

MODF

Reserved

SOD

SSM

SSI

Table 69.

SPICSR register description

Bit

Name

Function

7SPIF

Serial Peripheral Data Transfer Flag

This bit is set by hardware when a transfer has been completed. An interrupt is

generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an

access to the SPICSR register followed by a write or a read to the SPIDR register).

0: Data transfer is in progress or the flag has been cleared

1: Data transfer between the device and an external device has been completed.

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the

SPICSR register is read.

6WCOL

Write Collision status

This bit is set by hardware when a write to the SPIDR register is done during a

transmit sequence. It is cleared by a software sequence (see Figure 62).

0: No write collision occurred.

1: A write collision has been detected.

5OVR

SPI Overrun error

This bit is set by hardware when the byte currently being received in the shift register

is ready to be transferred into the SPIDR register while SPIF = 1 (see Overrun

condition (OVR) on page 132). An interrupt is generated if SPIE = 1 in SPICR

0: No overrun error

1: Overrun error detected

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