ST10F296 datasheet(220/346 Pages) STMICROELECTRONICS

220 / 346 page

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System reset

ST10F296E

220/346

Figure 78.

Asynchronous hardware reset (EA = 0)

Longer than Port 0 settling time + PLL synchronization (if needed, that is P0(15:13) changed). Longer than 500 ns to take

account of input filter on RSTIN pin.

Three to eight TCL depending on clock source selection.

20.3

Synchronous reset (warm reset)

A synchronous reset is triggered when the RSTIN pin is pulled low while the RPD pin is at

high level. To activate the internal reset logic of the device, the RSTIN pin must be held low,

at least, during 4 TCL (2 CPU clock periods). Refer to Section 20.1: Input filter on page 214

for details on minimum reset pulse duration. The I/O pins are set to high impedance and the

RSTOUT pin is driven low. Once the RSTIN level is detected, a short duration of 12 TCL

maximum (6 CPU clock periods) elapses, during which time pending internal hold states are

cancelled and the current internal access cycle (if any) is completed. The external bus cycle

is aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of the SYSCON

after a reset sequence.

RSTF

P0[15:13]

P0[12:2]

Transparent

Not t.

Transparent

Not t.

P0[1:0]

Not t.

Not transparent

3..8 TCL(2)

RST

Latching point of Port 0 for

system start-up configuration

RPD

ALE

(1)

Not transparent

(after filter)

RSTIN

≤500 ns

≥ 50 ns

≤500 ns

≥ 50 ns

8 TCL

3..4 TCL

Obsolete

Product(s)

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Product(s)

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