ST7MC1K2-Auto datasheet(320/371 Pages) STMICROELECTRONICS

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12.4.5

On-chip peripherals

12.5

Clock and timing characteristics

Subject to general operating conditions for VDD, fOSC, and TA.

12.5.1

General timings

Table 196.

On-chip peripherals

Symbol

Parameter

Conditions

Typ

Unit

IDD(TIM)

16-bit Timer supply current(1)

Data based on a differential IDD measurement between reset configuration (timer counter running at

fCPU/4) and timer counter stopped (only TIMD bit set). Data valid for one timer.

fCPU = 8MHz

VDD = 5.0V

µA

IDD(ART)

ART PWM supply current(2)

Data based on a differential IDD measurement between reset configuration (timer stopped) and timer

counter enable (only TCE bit set)

IDD(SPI)

SPI supply current(3)

Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent

SPI master communication at maximum speed (data sent equal to 55h). This measurement includes the

pad toggling consumption.

400

IDD(SCI)

SCI supply current(4)

Data based on a differential IDD measurement between SCI low power state (SCID = 1) and a permanent

SCI data transmit sequence.

400

IDD(MTC)

MTC supply current(5)

Data based on a differential IDD measurement between reset configuration (motor control disabled) and the

whole motor control cell enable in speed measurement mode. MCO outputs are not validated.

500

IDD(ADC)

ADC supply current when converting(6)

Data based on a differential IDD measurement between reset configuration and continuous A/D

conversions.

fADC = 4 MHz

400

IDD(op-amp) Op-amp supply current

(7)

Data based on a differential measurement between reset configuration (op-amp disabled) and amplification

of a sinewave (no load, AVCL =1, VDD =5V).

fCPU = 8 MHz

1500

Table 197.

General timings

Symbol

Parameter

Conditions

Min

Typ(1)

Data based on typical application software

Max

Unit

tc(INST)

Instruction cycle time

tCPU

fCPU = 8 MHz

250

375

1500

tv(IT)

Interrupt reaction time(2)

tv(IT) = ∆tc(INST) + 10

Time measured between interrupt event and interrupt vector fetch.

∆ t

c(INST) is the number of tCPU cycles

needed to finish the current instruction execution.

tCPU

fCPU = 8 MHz

1.25

2.75

µs

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