ST7MC1K2-Auto datasheet(276/371 Pages) STMICROELECTRONICS

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PWM control register (MPCR)

MPCR

Reset value: 0000 0000 (00h)

654

PMS

OVFU

OVFV

OVFW

CMS

PCP[2:0]

R/W

Table 144.

MPCR register description

Bit

Name

Function

PMS

PWM mode selection

0: Standard mode: bit b7 in the MCPxH register represents the extension bit

1: ‘8-bit’ mode: bit b7 (extension bit) in the MCPxH register is located in the MPCR

decreased to b15:b8 instead of b15:b3.

6OVFU

Phase U 100% duty cycle selection

0: Duty cycle defined by MCPUH:MCPUL register

1: Duty cycle set at 100% on phase U at next update event and maintained until the

next one. This bit is reset once transferred to the active register on update event.

5OVFV

Phase V 100% duty cycle selection

0: Duty cycle defined by MCPVH:MCPVL register

1: Duty cycle set at 100% on phase V at next update event and maintained until the

next one. This bit is reset once transferred to the active register on update event

4OVFW

Phase W 100% duty cycle selection

0: Duty cycle defined by MCPWH:MCPWL register

1: Duty cycle set at 100% on phase W at next update event and maintained until

the next one. This bit is reset once transferred to the active register on update

event.

3CMS

PWM counter mode selection

0: Edge-aligned mode

1: Center-aligned mode

2:0 PCP[2:0]

PWM counter prescaler value

This value divides the Fmtc frequency by N, where N is PCP[2:0] value. The

resulting frequency of the PWM counter input clock is shown below:

000: PWM counter input clock = Fmtc

001: PWM counter input clock = Fmtc/2

010: PWM counter input clock = Fmtc/3

011: PWM counter input clock = Fmtc/4

100: PWM counter input clock = Fmtc/5

101: PWM counter input clock = Fmtc/6

110: PWM counter input clock = Fmtc/7

111: PWM counter input clock = Fmtc/8

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