ST7MC1K2-Auto datasheet(248/371 Pages) STMICROELECTRONICS

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Figure 115. Channel manager output block diagram with PWM generator delivering three PWM

signals

The output of the current limitation comparator can be used when three PWM signals are enabled if the VOC1 bit = 0 in the

MCRA register.

If the PCN bit is reset, one of the three PWM signals (the one set by the compare U register pair) or the

output of the measurement window generator (depending on if the driving mode is voltage or current) is

used to provide six-step signals through the PWM manager (to drive a PM BLDC motor for instance).

In that case, DTE behaves like a standard bit (with multiple write capability). When the deadtime

generator is enabled (bit DTE = 1), the following restrictions are applied:

●

Channels are now grouped by pairs: channel[0:1], channel[2:3], channel[4:5]; a deadtime generator

is allocated to each of these pairs (see cautions below).

●

The input signal of the deadtime generator is the active output of the PWM manager for the

corresponding channel. For instance, if we consider the channel[0:1] pair, it may be either channel 0

or channel 1.

●

When both channels of a pair are inactive, the corresponding outputs also stay inactive (this is

mandatory to allow BEMF zero-crossing detection).

These restrictions are summarized in Table 111, which also summarizes the functionality of the deadtime

generator when the PCN bit is reset. 1 (PWM) means that the corresponding channel is active (1 in the

corresponding bit in the MPHST register), and a PWM signal is applied on it (using the MPAR register

and the OS[2:0] bits in MCRB register). PWM represents the complementary signals (although the duty

cycle is slightly different due to deadtime insertion). 0 means that the channel is inactive and 1 means

that the channel is active and a logic level 1 is applied on it (no PWM signal).

Dead

time

MDTG register

PWM generator signals

PCN bit = 1

OP[5:0] bits

MOE bit

MPOL register

MRCA register

Channel [1:0]

Channel [3:2]

Channel [5:4]

High frequency chopper

HFE[1:0] bits

HFRQ[2:0] bits

MREF register

CLI bit

CLIM bit

OCV bit

Dead

time

Dead

time

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