ST7MC1K2-Auto datasheet(237/371 Pages) STMICROELECTRONICS

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On-chip peripherals

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Current feedback amplifier

In both current and voltage mode, the current feedback from the motor can be amplified

before entering the comparator. This is done by an integrated op-amp that can be used

when the OAON bit is set in the OACSR register and the CFAV bit in the MREF register is

reset. This allows the three points of the op-amp to be accessed for a programmable gain.

The CFAV bit in the MREF register selects the MCCFI0 or OAZ(MCCFI1) pin as the

comparator input as shown in the following table.

If the amplifier is not used for current feedback, it can be used for other purposes. In this

case, the OAON bit in the OACSR register and the CFAV bit in the MREF register both have

to be set. This means that the current feedback has to be on the MCCFI0 pin to be directly

connected to the comparator and the OAP, OAN and OAZ (MCCFI1) pins can be used to

amplify another signal. Both the OAZ(MCCFI1) and MCCFI0 pins can be connected to an

ADC entry. See (Figure 107).

Note:

The MCCFI0 pin is not available in LQFP32 and LQFP44 devices. In this case, the CFAV bit

must be reset. The choice to use the op-amp or not is made with the OAON bit.

Measurement window

In current mode, the measurement window frequency can be programmed between 390Hz

and 50 kHz by the means of the SA[3:0] bits in the MPRSR register.

Note:

These frequencies are given for a 4 MHz peripheral input frequency for a BLDC drive (XT16,

XT8 bits in MCONF register).

In sensorless mode this measurement window can be used to detect BEMF zero crossing

events. Its width can be defined between 2.5

µs and 40µs as a minimum in sensorless mode

by the OT[3:0] bits in the MPWME register.

This sets the minimum off time of the PWM signal generated by this internal clock. This off

time can vary depending on the output of the current feedback comparator. In sensor mode

(SR = 1) and when the sampling for the Z event is done during the PWM ON time in

sensorless mode (SPLG bit is set in MCRC register and/or DS[3:0] bits with a value other

than 000 in MCONF register), there is no minimum OFF time required anymore, the

minimum off time is set automatically to 0µs and the OFF time of the PWM signal is

controlled only by the current regulation loop.

Table 104.

Comparator input selection

CFAV bit

Meaning

Select OAZ(MCCFI1) as the current comparator input

Select MCCFI0 as the current comparator input

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