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ST7LITE49K2 bảng dữ liệu(PDF) 175 Page - STMicroelectronics |
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ST7LITE49K2 bảng dữ liệu(HTML) 175 Page - STMicroelectronics |
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175 / 245 page  ST7LITE49K2 On-chip peripherals 175/245 Data register high (ADCDRH) Reset value: xxxx xxxx (xxh) Bits 7:0 = D[9:2] MSB of Analog Converted Value ADC control/data register low (ADCDRL) Reset value: 0000 00xx (0xh) Bits 7:5 = Reserved. Forced by hardware to 0. Bit 4 = AMPCAL Amplifier calibration bit This bit is set and cleared by software. It is advised to use this bit to calibrate the ADC when amplifier is ON. Setting this bit internally connects amplifier input to 0V. Hence, corresponding ADC output can be used in software to eliminate amplifier-offset error. 0: Calibration off 1: Calibration on (The input voltage of the amplifier is set to 0V) Bit 3 = SLOW Slow mode bit This bit is set and cleared by software. It is used together with the SPEED bit in the ADCCSR register to configure the ADC clock speed as shown on the table below. Bit 2 = AMPSEL Amplifier selection bit This bit is set and cleared by software. 0: Amplifier is not selected 1: Amplifier is selected Note: When AMPSEL=1 it is mandatory that fADC be less than or equal to 2 MHz. Bits 1:0 = D[1:0] LSB of analog converted value 7 0 D9 D8 D7 D6 D5 D4 D3 D2 Read only 7 0 0 0 0 AMPCAL SLOW AMPSEL D1 D0 Read/write Table 56. Configuring the ADC clock speed fADC (1) 1. The maximum allowed value of fADC is 4 MHz (see Section 13.11 on page 226) SLOW SPEED fCPU/2 0 0 fCPU 01 fCPU/4 1 x |
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