ST7LITE49K2 datasheet(157/245 Pages) STMICROELECTRONICS

157 / 245 page

ST7LITE49K2

On-chip peripherals

157/245

Figure 73.

Serial peripheral interface block diagram

11.6.4

Functional description

A basic example of interconnections between a single master and a single slave is

illustrated in Figure 74.

The MOSI pins are connected together and the MISO pins are connected together. In this

way data is transferred serially between master and slave (most significant bit first).

The communication is always initiated by the master. When the master device transmits

data to a slave device via MOSI pin, the slave device responds by sending data to the

master device via the MISO pin. This implies full duplex communication with both data out

and data in synchronized with the same clock signal (which is provided by the master device

via the SCK pin).

To use a single data line, the MISO and MOSI pins must be connected at each node (in this

case only simplex communication is possible).

Four possible data/clock timing relationships may be chosen (see Figure 77 on page 162)

but master and slave must be programmed with the same timing mode.

SPIDR

Read Buffer

8-Bit Shift Register

Write

Read

Data/Address Bus

SPI

SPIE

SPE

MSTR

CPHA

SPR0

SPR1

CPOL

SERIAL CLOCK

GENERATOR

MOSI

MISO

SCK

CONTROL

STATE

SPICR

SPICSR

Interrupt

request

MASTER

CONTROL

SPR2

SPIF WCOL

MODF

OVR

SSI

SSM

SOD

bit

ST7LITE49K2 bảng dữ liệu(PDF) 157 Page - STMicroelectronics

ST7LITE49K2 bảng dữ liệu(HTML) 157 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL