ST7LITE49K2 datasheet(152/245 Pages) STMICROELECTRONICS

152 / 245 page

On-chip peripherals

ST7LITE49K2

152/245

I2C status register 2 (I2CSR2)

Reset value: 0000 0000 (00h)

Bits 7:5 = Reserved. Forced to 0 by hardware.

Bit 4 = AF Acknowledge failure bit

This bit is set by hardware when no acknowledge is returned. An interrupt is generated

if ITE=1. It is cleared by software reading SR2 register or by hardware when the

interface is disabled (PE=0).

The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at

the same time.

0: No acknowledge failure

1: Acknowledge failure

Bit 3 = STOPF Stop detection bit (slave mode)

This bit is set by hardware when a Stop condition is detected on the bus after an

acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software

reading SR2 register or by hardware when the interface is disabled (PE=0).

The SCL line is not held low while STOPF=1.

0: No Stop condition detected

1: Stop condition detected

Bit 2 = ARLO Arbitration lost bit

This bit is set by hardware when the interface loses the arbitration of the bus to another

master. An interrupt is generated if ITE=1. It is cleared by software reading SR2

After an ARLO event the interface switches back automatically to Slave mode

(M/SL=0).

The SCL line is not held low while ARLO=1.

0: No arbitration lost detected

1: Arbitration lost detected

Note:

In a Multimaster environment, when the interface is configured in Master Receive mode it

does not perform arbitration during the reception of the Acknowledge Bit. Mishandling of the

ARLO bit from the I2CSR2 register may occur when a second master simultaneously

requests the same data from the same slave and the I2C master does not acknowledge the

data. The ARLO bit is then left at 0 instead of being set.

Bit 1 = BERR Bus error bit

This bit is set by hardware when the interface detects a misplaced Start or Stop

condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2

The SCL line is not held low while BERR=1.

0: No misplaced Start or Stop condition

1: Misplaced Start or Stop condition

STOPF

ARLO

BERR

GCAL

Read Only

ST7LITE49K2 bảng dữ liệu(PDF) 152 Page - STMicroelectronics

ST7LITE49K2 bảng dữ liệu(HTML) 152 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL