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ST7LITE49K2 bảng dữ liệu(PDF) 149 Page - STMicroelectronics

tên linh kiện ST7LITE49K2
Giải thích chi tiết về linh kiện  Communication interfaces
PDF  245 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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ST7LITE49K2 bảng dữ liệu(HTML) 149 Page - STMicroelectronics

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On-chip peripherals
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Bit 1 = STOP Generation of a Stop condition bit
This bit is set and cleared by software. It is also cleared by hardware in master mode.
Note: This bit is not cleared when the interface is disabled (PE=0).
●
In master mode:
0: No stop generation
1: Stop generation after the current byte transfer or after the current Start condition is
sent. The STOP bit is cleared by hardware when the Stop condition is sent.
●
In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode
the STOP bit has to be cleared by software.
Bit 0 = ITE Interrupt Enable bit
This bit is set and cleared by software and cleared by hardware when the interface is
disabled (PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 72 for the relationship between the events and the interrupt.
SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See
Figure 71) is detected.



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