SPC563M64L7 datasheet(24/48 Pages) STMICROELECTRONICS

24 / 48 page

Device overview

SPC563Mxx

24/48

Doc ID 13850 Rev 6

Note:

The calibration EBI must be configured in multiplexed mode when the extended Nexus trace

is used on the VertiCal Calibration Systemcalibration tool. This is because Nexus signals

and address lines of the calibration bus share the same balls in the calibration package.

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Memory controller with support for various memory types:

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Asynchronous/legacy flash and SRAM

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Bus monitor

–

User selectable

–

Programmable time-out period (with 8 external bus clock resolution)

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Configurable wait states (via chip selects)

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3 chip-select (Cal_CS[0], Cal_CS[2:3]) signals (Multiplexed with 2 most significant

address signals)

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2 write/byte enable (WE[0:1]/BE[0:1]) signals

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Configurable bus speed modes

–

system frequency

–

1/2 of system frequency

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1/4 of system frequency

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Optional automatic CLKOUT gating to save power and reduce EMI

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Selectable drive strengths; 10 pF, 20 pF, 30 pF, 50 pF

3.3.7

SIU

The SPC563Mxx SIU controls MCU reset configuration, pad configuration, external

interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset

operation. The reset configuration block contains the external pin boot configuration logic.

The pad configuration block controls the static electrical characteristics of I/O pins. The

GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.

The reset controller performs reset monitoring of internal and external reset sources, and

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