SPC560P40L3 datasheet(13/103 Pages) STMICROELECTRONICS

13 / 103 page

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Introduction

Doc ID 16100 Rev 7

13/103

1.5

Feature details

1.5.1

High performance e200z0 core processor

The e200z0 Power Architecture core provides the following features:

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High performance e200z0 core processor for managing peripherals and interrupts

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Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU

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Harvard architecture

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Variable length encoding (VLE), allowing mixed 16- and 32-bit instructions

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Results in smaller code size footprint

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Minimizes impact on performance

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Branch processing acceleration using lookahead instruction buffer

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Load/store unit

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1-cycle load latency

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Misaligned access support

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No load-to-use pipeline bubbles

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Thirty-two 32-bit general purpose registers (GPRs)

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Separate instruction bus and load/store bus Harvard architecture

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Hardware vectored interrupt support

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Reservation instructions for implementing read-modify-write constructs

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Long cycle time instructions, except for guarded loads, do not increase interrupt

latency

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Extensive system development support through Nexus debug port

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Non-maskable interrupt support

1.5.2

Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between three

master ports and three slave ports. The crossbar supports a 32-bit address bus width and a

32-bit data bus width.

The crossbar allows for two concurrent transactions to occur from any master port to any

slave port; but one of those transfers must be an instruction fetch from internal flash

memory. If a slave port is simultaneously requested by more than one master port,

arbitration logic will select the higher priority master and grant it ownership of the slave port.

All other masters requesting that slave port will be stalled until the higher priority master

completes its transactions. Requesting masters will be treated with equal priority and will be

granted access a slave port in round-robin fashion, based upon the ID of the last master to

be granted access.

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