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SPC560B64x bảng dữ liệu(PDF) 78 Page - STMicroelectronics

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Electrical characteristics
SPC560B54x/6x
78/133
DocID15131 Rev 9
Table 25. Reset electrical characteristics
Symbol
C
Parameter
Conditions(1)
Value
Unit
Min
Typ
Max
VIH
SR P
Input High Level CMOS
(Schmitt Trigger)
0.65VDD —VDD + 0.4
V
VIL
SR P
Input low Level CMOS
(Schmitt Trigger)
0.4
0.35VDD
V
VHYS
CC C
Input hysteresis CMOS
(Schmitt Trigger)
—0.1VDD
——
V
VOL
CC P Output low level
Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
0.1VDD
V
Push Pull, IOL = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V =
1(2)
0.1VDD
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
——
0.5
ttr
CC D
Output transition time output
pin(3) MEDIUM configuration
CL = 25 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
——
10
ns
CL = 50 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
——
20
CL = 100 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
——
40
CL = 25 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——
12
CL = 50 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——
25
CL = 100 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——
40
WFRST SR P RESET input filtered pulse
40
ns
WNFRST SR P RESET input not filtered pulse
1000
ns
|IWPU|CC
P
Weak pull-up current absolute
value
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
150
µA
DVDD = 5.0 V ± 10%, PAD3V5V = 0
10
150
P
VDD = 5.0 V ± 10%, PAD3V5V =
1(4)
10
250
1.
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2.
This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the
device reference manual).
3.
CL includes device and package capacitance (CPKG < 5 pF).
4.
The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.



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