SPC56EL70L5 datasheet(20/128 Pages) STMICROELECTRONICS

20 / 128 page

Introduction

SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5

20/128

DocID023953 Rev 5

1.5.19

System timer module (STM)

The STM implements the following features:



Up-counter with 4 output compare registers



OS task protection and hardware tick implementation per AUTOSAR(a) requirement

The STM is replicated for each processor.

1.5.20

Software watchdog timer (SWT)

This module implements the following features:



Fault tolerant output



Safe internal RC oscillator as reference clock



Windowed watchdog



Program flow control monitor with 16-bit pseudorandom key generation



Allows a high level of safety (SIL3 monitor)

The SWT module is replicated for each processor.

1.5.21

Fault collection and control unit (FCCU)

The FCCU module has the following features:



Redundant collection of hardware checker results



Redundant collection of error information and latch of faults from critical modules on

the device



Collection of self-test results



Configurable and graded fault control

–

Internal reactions (no internal reaction, IRQ, Functional Reset, Destructive Reset,

or Safe mode entered)

–

External reaction (failure is reported to the external/surrounding system via

configurable output pins)

1.5.22

System Integration Unit Lite (SIUL)

The SIUL controls MCU reset configuration, pad configuration, external interrupt, general

purpose I/O (GPIO), internal peripheral multiplexing, and system reset operation. The reset

configuration block contains the external pin boot configuration logic. The pad configuration

block controls the static electrical characteristics of I/O pins. The GPIO block provides

uniform and discrete input/output control of the I/O pins of the MCU.

a. Automotive Open System Architecture

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