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PM6675 bảng dữ liệu(PDF) 41 Page - STMicroelectronics

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PM6675 bảng dữ liệu(HTML) 41 Page - STMicroelectronics

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7.1.7
All ceramic capacitors application
Design of external feedback network depends on the output voltage ripple across the output
capacitors' ESR. If the ripple is great enough (at least 20mV), the compensation network
simply consists of a CINT capacitor.
Figure 21. Integrative compensation
The stability of the system firstly depends on the output capacitor zero frequency. It must be
verified that:
Equation 49
where k is a free design parameter greater than unity (k > 3) . It determines the minimum
integrator capacitor value CINT:
Equation 50
If the ripple on the COMP pin is greater than the integrator output dynamic (150mV), an
additional capacitor Cfilt could be added in order to reduce its amplitude. If q is the desired
attenuation factor of the output ripple, select:
CFILT
CINT
RINT
gm
+
-
VREF
VSNS
Ton One-shot
generator
Vr=0.9
V
PWM
Comparator
+
-
COMP
VOUT
Integrator
out
out
Zout
SW
C
R
2
k
f
k
f
π
=
>
Vo
Vref
f
k
f
2
g
C
Zout
SW
m
INT
π
>



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