UM1817 datasheet(17/58 Pages) STMICROELECTRONICS

17 / 58 page

DocID026902 Rev 3

17/58

UM1817

Hardware layout and configuration

2.5

Reset source

The reset signal of STM32091C-EVAL evaluation board is low active and the reset sources

include:

•

Reset button B1

•

Debugging tools from SWD connector CN10 and CN11

•

Daughterboard from CN7

•

Embedded ST-LINK/V2-1

•

RS-232 connector CN9 for ISP.

Note:

The jumper JP11 must be closed for RESET handled by pin 8 of the RS-232 connector CN9

(CTS signal). Refer to Section 2.8 for details.

2.6

Boot option

The STM32091C-EVAL evaluation board is able to boot from:

•

Embedded user Flash

•

System memory with boot loader for ISP

•

Embedded SRAM for debugging

The boot option is configured by setting one jumper cap on CN7 between pin 22 and pin 24

and one option bit (see Table 7).

The BOOT0 can also be configured via RS-232 connector CN9, as shown in Table 8.

SB14

PF1 is connected to 8MHz crystal when SB14 is open.

(Default setting)

PF1 is connected to extension connector CN7 when SB14 is closed. In such case

R56 must be removed to avoid disturbance due to the 8 Mhz quartz.

Table 6. 8MHz crystal X2 related solder bridges (continued)

Table 7. Boot related switch

Switch

configuration

bit12 in USER

OPTION BYTES

Boot from

CN7 pin 22 and

pin 24 opened

STM32091C-EVAL boot from User Flash. (Default setting)

CN7 pin 22 and

pin 24 closed by

jumper

STM32091C-EVAL boot from Embedded SRAM.

CN7 pin 22 and

pin 24 closed by

jumper

STM32091C-EVAL boot from System Memory.

UM1817 bảng dữ liệu(PDF) 17 Page - STMicroelectronics

UM1817 bảng dữ liệu(HTML) 17 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

bảng dữ liệu tải về

Link URL