TNETV2685FIBZUTA5 datasheet(42/191 Pages) TI1

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TMS320DM647

TMS320DM648

SPRS372H – MAY 2007 – REVISED APRIL 2012

www.ti.com

3.2.4

Priority Allocation (PRI_ALLOC)

Each of the masters (excluding the C64x+ Megamodule) is assigned a priority via the Priority Allocation

vying for the same endpoint. A value of 000b has the highest priority, while 111b has the lowest priority.

Note that the configuration SCR port on the data SCR is considered a single endpoint meaning priority will

be enforced when multiple masters try to access the configuration SCR. Priority is also enforced on the

configuration SCR side when a master (through the data SCR) tries to access the same endpoint as the

C64x+ Megamodule.

The Ethernet Subsystem and VLYNQ fields specify the priority of the Ethernet Subsystem and VLYNQ

peripherals, respectively. Similarly, the HOST field applies to the priority of the HPI and PCI peripherals.

Other master peripherals are not present in the PRI_ALLOC register as they have their own registers to

program their priorities. For more information on the default priority values in these peripheral registers,

see the device-compatible peripheral reference guides.

TI recommends that these priority registers be reprogrammed during device initialization.

Table 3-6. Default Master Priorities

MASTER

DEFAULT PRIORITY

EDMA3TC0

0 (EDMA CC QUEPRI Register)

EDMA3TC1

0 (EDMA CC QUEPRI Register)

EDMA3TC2

0 (EDMA CC QUEPRI Register)

EDMA3TC3

0 (EDMA CC QUEPRI Register)

64x+_DMAP

7 (C64x+ MDMAARBE.PRI Register bit field)

64x+_CFGP

1 (C64x+ MDMAARBE.PRI Register bit field)

Ethernet Subsystem

3 (PRI_ALLOC register)

VLYNQ

4 (PRI_ALLOC register)

UHPI

4 (PRI_ALLOC register)

PCI

4 (PRI_ALLOC register)

VICP

5 (PRI_ALLOC register)

Figure 3-4. Priority Allocation Register (PRI_ALLOC)

Reserved

R-0000000000001000

Reserved

VICP

VLYNQ

HOST

Ethernet Subsystem

R-0000

R/W-101

R/W-100

R/W-011

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Device Configuration

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