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TNETV6446AINZWT8 bảng dữ liệu(PDF) 94 Page - Texas Instruments |
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TNETV6446AINZWT8 bảng dữ liệu(HTML) 94 Page - Texas Instruments |
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94 / 227 page  PLLDIV1 PLLDIV2 1 0 Post−Div (/1) PLLM PLL 0 1 BPDIV CLKMODE CLKIN OSCIN PLLEN PLL2_SYSCLK1 (VPSS−VPBE) PLL2_SYSCLK2 (DDR2 PHY) PLL2_SYSCLKBP (DDR2 VTP) TMS320DM6446 SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com Figure 6-8. PLL2 Structure Block Diagram 6.3.1.4 Power and Sleep Controller (PSC) Module The Power and Sleep Controller (PSC) controls DM6446 device power by turning off unused power domains or gating off clocks to individual peripherals/modules. The PSC consists of a Global PSC (GPSC) and a set of Local PSCs (LPSCs). The GPSC contains memory mapped registers, power domain control, PSC interrupt control, and a state machine for each peripheral/module. An LPSC is associated with each peripheral/module and provides clock and reset control. The GPSC controls all of DM6446’s LPSCs. The ARM subsystem does not have an LPSC module. ARM sleep mode is accomplished through the wait for interrupt instruction. The LPSCs for DM6446 are shown in Table 6-5. The PSC register memory map is given in Table 6-6. For more details on the PSC, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14). Table 6-5. DM6446 LPSC Assignments LPSC PERIPHERAL/MODULE LPSC PERIPHERAL/MODULE LPSC PERIPHERAL/MODULE NUMBER NUMBER NUMBER 0 VPSS DMA 14 EMIFA 28 TIMER1 1 VPSS MMR 15 MMC/SD/SDIO 29 Reserved 2 EDMA3CC 16 Reserved 30 Reserved 3 EDMA3TC0 17 ASP 31 Reserved 4 EDMA3TC1 18 I2C 32 Reserved 5 EMAC 19 UART0 33 Reserved 6 EMAC Memory Controller 20 UART1 34 Reserved 7 MDIO 21 UART2 35 Reserved 8 Reserved 22 SPI 36 Reserved 9 USB 23 PWM0 37 Reserved 10 ATA/CF 24 PWM1 38 Reserved 11 VLYNQ 25 PWM2 39 C64x+ CPU 12 HPI 26 GPIO 40 VICP 13 DDR2 Memory Controller 27 TIMER0 94 Peripheral and Electrical Specifications Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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