TNETV6446AINZWT datasheet(90/227 Pages) TI1

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DDDSP

DDXX

(A)

Note A:DV

denotesallI/Osupplies.

DDXX

TMS320DM6446

SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

www.ti.com

Table 6-1. Core Supply Power-On Timing Requirements for DSP Host-Boot Mode (see Figure 6-4)

A-513,

-594,

NO.

UNIT

-810

MIN

MAX

td(CVDD-CVDDDSP)

Delay time, CVDD supply ready to CVDDDSP supply ramp start

(1)

In Host-Boot mode, the CVDDDSP supply must be powered up prior to closing (enabling) the shorting switch between the ALWAYS ON

and DSP power domains.

Figure 6-4. DSP Host-Boot Mode Core Supply Timings

Once the CVDD supply has been powered up, the I/O supplies may be powered up. Table 6-2 and

Figure 6-5 show the power-on sequence timing requirements for the Core vs. I/O power-up. DVDDXX is

used to denote all I/O supplies. Note: the DVDDXX supply power-up is specified relative to the CVDD supply

power-up, not the CVDDDSP supply.

Table 6-2. I/O Supply Power-On Timing Requirements (see Figure 6-5)

A-513,

-594,

NO.

UNIT

-810

MIN

MAX

td(CVDD-DVDD)

Delay time, CVDD supply ready to DVDDXX supply ramp start

100

Figure 6-5. I/O Supply Timings

There is not a specific power-up sequence that must be followed with respect to the order of the power-up

of the DVDD18, DVDDR2, and DVDD33 supplies. Once the CVDD supply is powered up and the td(CVDD-DVDDXX)

specification is met, the DVDD18, DVDDR2, and DVDD33 supplies may be powered up in any order of

preference. All other supplies may also be powered up in any order of preference once the td(CVDD-DVDDXX)

specification has been met.

Peripheral and Electrical Specifications

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