TNETV1644ZDU6 datasheet(112/306 Pages) TI1

112 / 306 page

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Table 3-21. Multiplexed Pins on DM6437 (continued)

SIGNAL

PINMUX DESCRIPTION

ZWT

ZDU

NAME

PINMUX GROUP

CONTROLLED BY PINMUX BIT FIELDS

NO.

YI4(CCD4)/GP[40]

D14

C18

EMIFA/VPSS Sub-Block 0

CCDCSEL

YI3(CCD3)/GP[39]

B14

A16

EMIFA/VPSS Sub-Block 0

CCDCSEL

YI2(CCD2)/GP[38]

C14

B17

EMIFA/VPSS Sub-Block 0

CCDCSEL

YI1(CCD1)/GP[37]

B15

B18

EMIFA/VPSS Sub-Block 0

CCDCSEL

YI0(CCD0)/GP[36]

C15

B19

EMIFA/VPSS Sub-Block 0

CCDCSEL

C_WE/EM_R/W/GP[35]

D13

C17

EMIFA/VPSS Sub-Block 0

AEM, CWENSEL

C_FIELD/EM_A[21]/GP[34]

D12

C16

EMIFA/VPSS Sub-Block 0

AEM, CFLDSEL

HSYNC/EM_CS5/GP[33]

F19

J22

EMIFA/VPSS Sub-Block 1

CS5SEL

VSYNC/EM_CS4/GP[32]

E19

H22

EMIFA/VPSS Sub-Block 1

CS4SEL

VCLK/GP[31]

D19

G22

EMIFA/VPSS Sub-Block 1

VENCSEL

VPBECLK/GP[30]

G19

K22

EMIFA/VPSS Sub-Block 1

VPBECKEN

YOUT7/GP[29]

H15

K21

EMIFA/VPSS Sub-Block 1

VENCSEL

YOUT6/GP[28]

H16

J21

EMIFA/VPSS Sub-Block 1

VENCSEL

YOUT5/GP[27]

H17

L19

EMIFA/VPSS Sub-Block 1

VENCSEL

YOUT4/GP[26]/(FASTBOOT)

G17

K19

EMIFA/VPSS Sub-Block 1

VENCSEL

YOUT3/GP[25]/(BOOTMODE3)

G16

H21

EMIFA/VPSS Sub-Block 1

VENCSEL

YOUT2/GP[24]/(BOOTMODE2)

G15

L20

EMIFA/VPSS Sub-Block 1

VENCSEL

YOUT1/GP[23]/(BOOTMODE1)

F15

K20

EMIFA/VPSS Sub-Block 1

VENCSEL

YOUT0/GP[22]/(BOOTMODE0)

F18

J20

EMIFA/VPSS Sub-Block 1

VENCSEL

COUT7/EM_D[7]/GP[21]

F17

H20

EMIFA/VPSS Sub-Block 1

AEM, VENCSEL

COUT6/EM_D[6]/GP[20]

F16

F21

EMIFA/VPSS Sub-Block 1

AEM, VENCSEL

COUT5/EM_D[5]/GP[19]

E17

F22

EMIFA/VPSS Sub-Block 1

AEM, VENCSEL

COUT4/EM_D[4]/GP[18]

E18

G21

EMIFA/VPSS Sub-Block 1

AEM, VENCSEL

COUT3/EM_D[3]/GP[17]

E16

F20

EMIFA/VPSS Sub-Block 1

AEM, VENCSEL

COUT2/EM_D[2]/GP[16]

D17

E22

EMIFA/VPSS Sub-Block 1

AEM, VENCSEL

COUT1/EM_D[1]/GP[15]

D18

G20

EMIFA/VPSS Sub-Block 1

AEM, VENCSEL

COUT0/EM_D[0]/GP[14]

D16

E21

EMIFA/VPSS Sub-Block 1

AEM, VENCSEL

LCD_OE/EM_CS3/GP[13]

C18

D22

EMIFA/VPSS Sub-Block 1

CS3SEL

G0/EM_CS2/GP[12]

C19

C22

EMIFA/VPSS Sub-Block 1

AEM, RGBSEL

B0/LCD_FIELD/EM_A[3]/GP[11]

B18

D21

EMIFA/VPSS Sub-Block 1

AEM, RGBSEL

R0/EM_A[4]/GP[10]/(AEAW2/PLLMS2)

A17

B21

EMIFA/VPSS Sub-Block 1

AEM, RGBSEL

G1/EM_A[1]/(ALE)/GP[9]/

A16

B20

EMIFA/VPSS Sub-Block 1

AEM, RGBSEL

(AEAW1/PLLMS1)

B1/EM_A[2]/(CLE)/GP[8]/

B16

A20

EMIFA/VPSS Sub-Block 1

AEM, RGBSEL

(AEAW0/PLLMS0)

R1/EM_A[0]/GP[7]/(AEM2)

B17

C21

EMIFA/VPSS Sub-Block 1

AEM, RGBSEL

R2/EM_BA[0]/GP[6]/(AEM1)

C17

E20

EMIFA/VPSS Sub-Block 1

AEM, RGBSEL

B2/EM_BA[1]/GP[5]/(AEM0)

C16

C20

EMIFA/VPSS Sub-Block 1

AEM, RGBSEL

EM_A[12]/PCBE3/GP[89]

D10

B12

EMIFA/VPSS Sub-Block 3

PCIEN, AEM

EM_A[11]/AD24/GP[90]

C10

C12

EMIFA/VPSS Sub-Block 3

PCIEN, AEM

EM_A[10]/AD23/GP[91]

B11

EMIFA/VPSS Sub-Block 3

PCIEN, AEM

EM_A[9]/PIDSEL/GP[92]

C11

EMIFA/VPSS Sub-Block 3

PCIEN, AEM

EM_A[8]/AD21/GP[93]

A11

EMIFA/VPSS Sub-Block 3

PCIEN, AEM

EM_A[7]/AD22/GP[94]

C10

EMIFA/VPSS Sub-Block 3

PCIEN, AEM

EM_A[6]/AD20/GP[95]

B10

EMIFA/VPSS Sub-Block 3

PCIEN, AEM

EM_A[5]/AD19/GP[96]

A10

EMIFA/VPSS Sub-Block 3

PCIEN, AEM

Device Configurations

112

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