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TNETV1647GSTZWT bảng dữ liệu(PDF) 213 Page - Texas Instruments |
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TNETV1647GSTZWT bảng dữ liệu(HTML) 213 Page - Texas Instruments |
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213 / 236 page ![]() MRCLK (Input) 1 2 MRXD3−MRXD0, MRXDV, MRXER (Inputs) 1 MTCLK (Input) MTXD3−MTXD0, MTXEN (Outputs) TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-92. Timing Requirements for EMAC MII Receive 10/100 Mbit/s(1) (see Figure 6-67) 1.05 V and 1.2 V NO. UNIT MIN MAX 1 tsu(MRXD-MRCLKH) Setup time, receive selected signals valid before MRCLK high 8 ns 2 th(MRCLKH-MRXD) Hold time, receive selected signals valid after MRCLK high 8 ns (1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER. Figure 6-67. EMAC Receive Interface Timing Table 6-93. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s(1) (see Figure 6-68) 1.05 V and 1.2 V NO. UNIT MIN MAX 1 td(MTCLKH-MTXD) Delay time, MTCLK high to transmit selected signals valid 5 25 ns (1) Transmit selected signals include: MTXD3-MTXD0, and MTXEN. Figure 6-68. EMAC Transmit Interface Timing Copyright © 2006–2010, Texas Instruments Incorporated Peripheral and Electrical Specifications 213 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
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