TNETV1647GSTZWT datasheet(206/236 Pages) TI1

206 / 236 page

TMS320DM6441

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

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Table 6-85. Switching Characteristics Over Recommended Operating Conditions for ASP(1) (2)

(see Figure 6-64)

1.05 V and 1.2 V

NO.

PARAMETER

UNIT

MIN

MAX

tc(CKRX)

Cycle time, CLKR/X

CLKR/X int

38.5(3)

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X int

C - 1(4)

C + 1(4)

td(CKRH-FRV)

Delay time, CLKR high to internal FSR valid

CLKR int

-2.1

CLKX int

-1.7

td(CKXH-FXV)

Delay time, CLKX high to internal FSX valid

CLKX ext

1.7

14.4

CLKX int

-3.9

Disable time, DX high impedance following last data

tdis(CKXH-DXHZ)

bit from CLKX high

CLKX ext

2.1

CLKX int

-3.9 + D1(5)

4 + D2(5)

td(CKXH-DXV)

Delay time, CLKX high to DX valid

CLKX ext

2.1 + D1(5)

14.5 + D2(5)

Delay time, FSX high to DX valid

FSX int

-2.3 + D1(6)

4 + D2(6)

td(FXH-DXV)

ONLY applies when in data

FSX ext

1.9 + D1(6)

12.1 + D2(6)

delay 0 (XDATDLY = 00b) mode

(1)

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2)

Minimum delay times also represent minimum output hold times.

(3)

Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times

are based on internal logic speed; the maximum usable speed may be lower due to EDMA3 limitations and AC timing requirements.

(4)

C = H or L

S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency [SYSCLK1])

S = sample rate generator input clock = Not Supported if CLKSM = 0 (no CLKS pin on DM6441)

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

CLKGDV should be set appropriately to ensure the ASP bit rate does not exceed the maximum limit [see footnote (3) above].

(5)

Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 4P, D2 = 8P

(6)

Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 4P, D2 = 8P

206

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