TNETV1647GSTZWT datasheet(181/236 Pages) TI1

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PCLK

(Positive Edge Clocking)

13, 31

PCLK

(Negative Edge Clocking)

11, 29

VCTL(A)

A. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE

B. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]

VDATA(B)

14, 32

12, 30

VPBECLK

TMS320DM6441

www.ti.com

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

Table 6-62. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and

Data Output With Respect to PCLK and VPBECLK(1) (see Figure 6-52)

1.05 V

1.2 V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

td(PCLK-VCTLV)

Delay time, PCLK edge to VCTL valid

13.3

td(PCLK-VCTLIV)

Delay time, PCLK edge to VCTL invalid

td(PCLK-VDATAV)

Delay time, PCLK edge to VDATA valid

13.3

td(PCLK-VDATAIV)

Delay time, PCLK edge to VDATA invalid

td(VPBECLK-VCTLV)

Delay time, VPBECLK rising edge to VCTL valid

13.3

td(VPBECLK-VCTLIV)

Delay time, VPBECLK rising edge to VCTL invalid

td(VPBECLK-VDATAV)

Delay time, VPBECLK rising edge to VDATA valid

13.3

td(VPBECLK-VDATAIV)

Delay time, VPBECLK rising edge to VDATA invalid

(1)

PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising

edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced.

Figure 6-52. VPBE Output Timing With Respect to PCLK and VPBECLK

Peripheral and Electrical Specifications

181

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