TNETV1647GSTZWT datasheet(148/236 Pages) TI1

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TMS320DM6441

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

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6.11.2.2 ATA/CF Multiword DMA Timing

Table 6-40. Timings for ATA/CF Module — Multiword DMA AC Timing(1) (2) (see Figure 6-27)

1.05 V and 1.2 V

NO.

MODE

UNIT

MIN

MAX

Cycle time

0-2

(DMASTB + DMARCVR + 2)P - 0.5

DIOW/DIOR active low pulse duration

0-2

(DMASTB + 1)P - 1

150

DIOR data access, DIOR falling edge to DD[15:0]

valid

DIOR data hold time, DD[15:0] valid after DIOR

0-2

rising edge

DIOW/DIOR data setup time, DD[15:0] (OUT) valid

0-2

(DMASTB)P

before DIOW/DIOR rising edge

100

DIOW/DIOR data setup time, DD[15:0] (IN) valid

before DIOW/DIOR rising edge

DIOW data hold time, DD[15:0] valid after DIOW

0-2

(HWNHLD + 1)P + 1

rising edge

DMACK to DIOW/DIOR setup

0-2

(DMARCVR + 1)P - 1.7

DIOW/DIOR to DMACK hold

0-2

5P - 5.9

tKR

DIOR negated pulse width

0-2

(DMARCVR + 1)P - 1

tKW

DIOW negated pulse width

0-2

(DMARCVR + 1)P - 1

120

tLR

DIOR to DMARQ delay

0-1

tLW

DIOW to DMARQ delay

ATA_CSx valid to DIOW/DIOR setup

0-2

(DATRCVR)P - 1.7

ATA_CSx valid after DIOW/DIOR rising edge hold

0-2

5P - 1.7

DMACK to read data (DD[15:0]) released

1-2

(1)

P = SYSCLK5 period, in ns, for ATA. For example, when running the DSP CPU at 405 MHz, use P = 14.8 ns.

(2)

DMASTB equals the value programmed in the DMASTBxP bit field in the DMASTB register. DMARCVR equals the value programmed

in the DMARCVRxP bit field in the DMARCVR register. HWNHLD equals the value programmed in the HWNHLDxP bit field in the

MISCCTL register. For more detailed information, see the TMS320DM644x DMSoC ATA Controller User's Guide (literature number

SPRUE21).

148

Peripheral and Electrical Specifications

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