DAC5682Z datasheet(13/66 Pages) TI1

13 / 66 page

DAC5682Z

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SLLS853F – AUGUST 2007 – REVISED JANUARY 2015

Electrical Characteristics (Digital Specifications) (continued)

over recommended operating free-air temperature range, AVDD, IOVDD = 3.3 V, CLKVDD, DVDD = 1.8 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Setup time, SDIO valid to

ts(SDIO)

rising edge of SCLK

Hold time, SDIO valid to

th(SDIO)

rising edge of SCLK

t(SCLK)

Period of SCLK

100

t(SCLKH)

High time of SCLK

t(SCLKL)

Low time of SCLK

Data output delay after

td(Data)

falling edge of SCLK

Minimum RESETB pulse

tRESET

width

CLOCK INPUT (CLKIN/CLKINC)

Duty cycle

50%

Differential voltage(3)

0.4

CLKIN/CLKINC input

CLKVDD

common mode

÷2

PHASE LOCKED LOOP

DAC output at 600 kHz offset, 100 MHz, 0-dBFS tone,

2X4, fDATA = 250 MSPS, CLKIN/C = 250 MHz,

–125

PLL_m = '00111', PLL_n = '001', VCO_div2 = 0,

PLL_range = '1111', PLL_gain = '00'

Phase noise

dBc/ Hz

DAC output at 6 MHz offset, 100 MHz, 0-dBFS tone,

2X4, fDATA = 250 MSPS, CLKIN/C = 250 MHz,

–146

PLL_m = '00111', PLL_n = '001', VCO_div2 = 0,

PLL_range = '1111', PLL_gain = '00'

(3)

Driving the clock input with a differential voltage lower than 1V will result in degraded performance.

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