TNETV2665FIDZWT7 datasheet(94/249 Pages) TI1

94 / 249 page

TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

www.ti.com

Table 3-18. PINMUX1 Register Description (continued)

Bit

Field Name

Description

Pins Controlled

Reserved. For proper device operation, the user should only write "0" to this bit

RSV

–

(default).

Host Block Pin Select.

Host Block:

If EMAC operation is desired, EMAC must be placed in reset before

VLYNQ_CLOCK/PCICLK/GP[57]

programming PINMUX1. HOSTBK or PINMUX0.RMII to select EMAC pins.

HD0/VLYNQ_SCRUN/AD18/GP[58]

HD1/VLYNQ_RXD0/AD16/GP[59]

PCIEN = 0 and HOSTBK = 000: GPIO Mode (default if PCIEN = 0).

HD2/VLYNQ_RXD1/AD17/GP[60]

Pins function as GPIO (GP[83:57]).

HD3/VLYNQ_RXD2/PCBE2/GP[61]

HD4/VLYNQ_RXD3/PFRAME/GP[62]

PCIEN = 0 and HOSTBK = 001: HPI + 1 GPIO Mode.

HD5/VLYNQ_TXD0/PIRDY/GP[63]

Pins function as HPI and GPIO (GP[57]).

HD6/VLYNQ_TXD1/PTRDY/GP[64]

PCIEN = 0 and HOSTBK = 010: VLYNQ + 17 GPIO Mode.

HD7/VLYNQ_TXD2/PDEVSEL/GP[65]

Pins function as VLYNQ (VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0],

HD8/VLYNQ_TXD3/PPERR/GP[66]

VLYNQ_TXD[3:0]), and GP[83:67].

HD9/MCOL/PSTOP/GP[67]

HD10/MCRS/PSERR/GP[68]

PCIEN = 0 and HOSTBK = 011: VLYNQ + MII + MDIO Mode.

HD11/MTXD3/PCBE1/GP[69]

Pins function as VLYNQ (VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0],

HD12/MTXD2/PPAR/GP[70]

VLYNQ_TXD[3:0]), MII (TXCLK, CRS, COL, TXD[3:0], RXVD, TXEN, RXER,

6:4

HOSTBK

HD13/MTXD1/AD14/GP[71]

RXCLK, RXD[3:0]), and MDIO (MDIO, MDC).

HD14/MTXD0/AD15/GP[72]

When EMAC(MII) is selected, EMAC(RMII) must not be selected.

HD15/MTXCLK/AD12/GP[73]

PINMUX0.RMII must be set to 0.

HHWIL/MRXDV/AD13/GP[74]

HCNTL1/MTXEN/AD11/GP[75]

PCIEN = 0 and HOSTBK = 100: MII + MDIO +10 GPIO Mode.

HCNTL0/MRXER/AD10/GP[76]

Pins function as MII (TXCLK, CRS, COL, TXD[3:0], RXVD, TXEN, RXER,

HR/W/MRXCLK/AD8/GP[77]

RXCLK, RXD[3:0]), MDIO (MDIO, MDC), and GP[66:57].

HDS2/MRXD0/AD9/GP[78]

When EMAC(MII) is selected, EMAC(RMII) must not be selected.

HDS1/MRXD1/AD7/GP[79]

PINMUX0.RMII must be set to 0.

HRDY/MRXD2/PCBE0/GP[80]

HCS/MDCLK/AD5/GP[81]

PCIEN = 1 and HOSTBK = 000: PCI Mode (default if PCIEN = 1).

HINT/MRXD3/AD6/GP[82]

Pins function as PCI pins: PCICLK, PCBE2, PCBE1, PCBE0, PFRAME,

HAS/MDIO/AD3/GP[83]

PIDRDY, PTRDY, PDEVSEL, PPER, PSTOP, PSERR, PPAR, AD[18:5], and

AD03.

The combination of PINMUX1 fields PCIEN and

HOSTBK select the function of these 27 pins.

All other PCIEN and HOSTBK combinations reserved.

Reserved. For proper device operation, the user should only write "0" to this bit

3:1

RESERVED

–

(default).

Device Configurations

Submit Documentation Feedback

Product Folder Link(s): TMS320C6424

TNETV2665FIDZWT7 bảng dữ liệu(PDF) 94 Page - Texas Instruments

TNETV2665FIDZWT7 bảng dữ liệu(HTML) 94 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL