L99MD01 datasheet(26/54 Pages) STMICROELECTRONICS

26 / 54 page

Functional description of the SPI

L99MD01

26/54

Doc ID 17242 Rev 6

Figure 9.

Indication of the global error flag on SDO when CSN is low and SCK is stable.

The bit 0 of the <Global Status Byte> is a combination of an under/overvoltage warning and

a software warning: If the bit 5 is one (this is the standard after a correct SPI

communication), bit 0 is the logical OR of all under- and overvoltage status bits.

On the other hand, if there has been an SPI communication error or a chip reset (bit 5 is

zero), then bit 0 gives a better indication about the SPI error: An SDI stuck-at error leads to

a software reset and sets bit 0, while a clock pulse error only sets the communication error

bit, clears bit 5 and clears also bit 0. This leads to the following table of possible states

(assuming there is no under/overvoltage, overcurrent, openload or thermal error):

Writing to the selected data input register is only enabled if exactly one frame length is

transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are

counted within one frame, the complete frame is ignored and a SPI frame error is signaled in

the Global Status register. This safety function is implemented to avoid an unwanted

activation of output stages by a wrong communication frame.

Table 22.

Reset

State

Description

Global status

EN = 0 (power on reset)

All registers reset

Outputs switched off (3-state)

1000 0000

Clock cycles != 24

Ignore frame

No reset

1100 0000

SDI always 0

Software reset

Outputs switched off

1100 0001

SDI always 1

Software reset

Outputs switched off

1100 0001

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