PC87364-XXXSLASHVLA datasheet(67/180 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.16.3

Logical Device 7 (GPIO) Configuration

Table 28 lists the configuration registers which affect the GPIO. Only the last three registers (F0h - F2h) are described here.

See Sections 2.2.3 and 2.2.4 for a detailed description of the others.

Table 28. GPIO Conﬁguration Register

Figure shows the organization of these registers.

Figure 7. Organization of GPIO Pin Registers

Index

Conﬁguration Register or Action

Type

Reset

30h

Activate. See also bit 7 of the SIOCF1 register.

R/W

00h

60h

Base Address MSB register

R/W

00h

61h

Base Address LSB register. Bits 3-0 (for A3-0) are read only, 0000b.

R/W

00h

70h

Interrupt Number

R/W

00h

71h

Interrupt Type. Bit 1 is read/write. Other bits are read only.

R/W

03h

74h

Report no DMA assignment

04h

75h

Report no DMA assignment

04h

F0h

GPIO Pin Select register

R/W

00h

F1h

GPIO Pin Conﬁguration register

R/W

00h

F2h

GPIO Pin Event Routing register

R/W

00h

GPIO Pin

Conﬁguration Register

Pin Select

Port Select

Port 0, Pin 0

GPIO Pin Select Register

GPIO Pin Event

Routing Register

Port 0, Pin 7

Port 0

Port 4

Pin 0

Pin 7

Port 1, Pin 0

Port 2, Pin 0

Port 3, Pin 0

Port 4, Pin 0

Port 0

Pin 0

Pin 7

Port 1

Port 4

Port 0, Pin 0

Port 1, Pin 0

Port 4, Pin 0

Port 0, Pin 7

Conﬁguration Registers

(Index F0h)

(Index F1h)

(Index F2h)

Event Routing

Registers

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