PC97338VLJ datasheet(190/221 Pages) NSC

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6.0 DMA and Interrupt Mapping

The Chip provides Plug and Play support.

6.1

DMA SUPPORT

6.1.1

Legacy Mode

Table 98 shows the conditions under which DMA re-

quest signals are put in TRI-STATE, in legacy mode.

For each DMA signal to be put in TRI-STATE, every

column must have one true condition. If no condition

is true in any one column, the signal is not put in TRI-

STATE.

6.1.2

Plug and Play Mode

The Chip allows the Floppy Disk Controller (FDC), the

parallel port and SCC2 to be connected to three 8-bit

DMA channels.

It is illegal to configure a pair of DMA signals to more

than one DMA source.

A pair of DMA signals may be configured to a specific

device only when the device is disabled.

Upon reset, DRQ2 and DACK2 are used by the FDC.

A DRQ line is in TRI-STATE and the DACK line input

is blocked to 1, when any of the following conditions

is true:

• When no device is mapped to the DMA channel.

• When the device mapped to the DMA channel is

inactive.

In Plug and Play mode, this condition is true for all

devices.

In Legacy mode, this condition is true only for

SCC2 and the parallel port, controlled by bit 2 of

the FER register and bit 2 of the PCR register, re-

spectively.

• When the device mapped to the DMA channel

floats its DRQ line.

Table 99 shows the conditions that put DMA request

signals in TRI-STATE, in Plug and Play mode. For

each DMA signal to be put in TRI-STATE, every col-

umn must have one true condition. If no condition is

true in any one column, the signal is not put in TRI-

STATE.

TABLE 98. DMA Support in Legacy Mode

TABLE 99. DMA Support in Plug and Play Mode

DMA Signal

Conditions for DRQx

a to be in TRI-STATE

Parallel Port

FDC

SCC2

DRQx

a. x = 0, 1 or 2

DRQx

a not selected

bit 2 of PCR = 0

bit 2 of PCR = 1

and bit 3 of ECR =0

DRQx

a not selected

bit 3 of DOR = 0

and bit 7 of ASC = 1

DRQx

a not selected

bit 2 of FER. = 0

DMA Signal

Conditions for DRQx

a to be in TRI-STATE

Parallel Port

FDC

SCC2

DRQx

a. x = 0, 1 or 2

DRQx

a not selected

bit 0 of FER = 0

bit 2 of PCR = 0

bit 2 of PCR = 1

and bit 3 of ECR =0

DRQx

a not selected

bit 3 of FER = 0

bit 3 of DOR = 0

and bit 7 of ASC = 1

DRQx

a not selected

bit 2 of FER = 0

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