STCF04 datasheet(18/43 Pages) STMICROELECTRONICS

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Detailed description

STCF04

18/43

Doc ID 022927 Rev 3

Data transmission from the main microprocessor to the STCF04 and vice versa takes place

through the 2 I²C bus interface wires, consisting of the two lines SDA and SCL (pull-up

resistors to a positive supply voltage must be externally connected).

8.1.8

Data validity

As shown in

Figure 5, the data on the SDA line must be stable during the high period of the

clock. The HIGH and LOW state of the data line can only change when the clock signal on

the SCL line is LOW.

8.1.9

START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. As shown in

Figure 6, a

START condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The STOP

condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition

must be sent before each START condition.

Figure 5.

Data validity on the I²C bus

CS11340

Figure 6.

Timing diagram on I²C bus

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