PC97338 datasheet(58/221 Pages) NSC

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tual hardware selection is determined by bits 7-4

and it is software’s responsibility to keep bits 2-0

and 7-4 in synchronization (if desired).

In Legacy mode, these bits are ignored and paral-

lel port interrupt mapping is controlled by bits 1,0

of the FAR register, bit 3 of the PTR register and

bit 0 of the ASC register.

2.3.20 Plug and Play Configuration 1

This register allows configurable mapping of the

SCC’s interrupt onto the ISA interrupts. Upon reset,

PNP1 is initialized to 00000000.

In Legacy mode, this register is ignored and the

UART interrupt mapping is controlled via bits 7-2 of

the FAR register.

FIGURE 21. PNP1 Register Bitmap

Bits 3-0 - SCC1 Interrupt Mapping

SCC1 interrupt mapping in Plug and Play mode.

Upon reset these bits are initialized to 0000.

These bits are defined and handled identically to

bits 4,5,6 and 7 of the parallel port in the Plug and

Play Configuration 0 Register (PNP0), Index 1Bh.

Bits 7-4 - SCC2 Interrupt Mapping

SCC2 interrupt mapping in Plug and Play mode.

Upon reset these bits are initialized to 0000.

These bits are defined and handled identically to

bits 4,5,6 and 7 of the parallel port in the Plug and

Play Configuration 0 Register (PNP0), Index 1Bh.

2.3.21 SuperI/O Chip Configuration

Undefined value when out of reset. This register con-

trols the following.

FIGURE 22. SCF2 Register Bitmap

Bits 1,0 - VLD0,1

These bits determine the state of bit 5 in the FDC

Tape Drive Register (TDR), when either Automatic

Media Sense TDR or Enhanced TDR is configured

(bit 0 of FCR = 0 or bit 2 of ASC = 1).

Bit 5 of TDR holds VLD0 bit value when two floppy

disk drives mode is configured (bit 4 of FER is 0)

and drive 0 is accessed. Bit 5 of TDR holds VLD1

bit value when two floppy disk drives mode is con-

figured (bit 4 of FER is 0) and drive 1 is accessed.

Otherwise, bit 5 of TDR holds 1.

Upon reset, these bits are undefined.

TABLE 22. TDR Bit 5 Values

Bits 3-2 - Reserved

These bits are reserved.

SCC1 Interrupt

SCC2 Interrupt Mapping

543

Reset

Required

(PNP1)

Plug and Play Configuration

Index 1Ch

Mapping

Drive Accessed

SCF2

TDR

Bit 1

Bit 0

Bit 5

None

543

Reset

Required

Index 40h

SuperI/O Chip

VLD1,0

Reserved

SCC1 Bank Select Enable

SCC2 Normal Power Mode

SCC2 is Busy

SCC2 Bank Select Enable

Configuration

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