PC87311A datasheet(49/78 Pages) NSC

49 / 78 page

60 Serial Ports (Continued)

TABLE 6-2 PC87311A Register Summary for an Individual UART Channel

0DLABe0

1DLABe0

0DLABe1

1DLABe1

Bit

Receiver

Buffer

(Read

Only)

Transmitter

Holding

(Write

Only)

Interrupt

Enable

Interrupt

(Read

Ident

Only)

Control

Line

MODEM

Control

Status

Line

MODEM

Status

(Note 4)

Scratch

Pad

Divisor

Latch

(LS)

Divisor

Latch

(MS)

RBR

THR

IER

IIR

LCR

MCR

LSR

MSR

SCR

DLL

DLM

Data Bit 0

Enable

‘‘0’’ if

Word

Data

Delta

Bit 0

Bit 8

(Note 1)

Received

Interrupt

Length

Terminal

Ready

Clear

Data

Pending

Select

Ready

(DR)

to Send

Available

Bit 0

(DTR)

Interrupt

Data Bit 1

Enable

Interrupt

Word

Request

Overrun

Delta

Bit 1

Bit 9

Transmitter

Length

to Send

Error

Data

Holding

Bit

Select

(RTS)

(OE)

Set

Bit 1

Ready

Empty

Interrupt

Data Bit 2

Enable

Interrupt

Number of

Out1

Parity

Trailing

Bit 2

Bit 10

Receiver

Stop Bits

Bit

Error

Edge Ring

Line Status

Bit

(PE)

Indicator

Interrupt

Data Bit 3

Enable

Parity

IRQ

Framing

Delta

Bit 3

Bit 11

MODEM

Enable

Error

Data

Status

(Note 3)

(FE)

Carrier

Interrupt

Detect

Data Bit 4

Even Parity

Loop

Break

Clear to

Bit 4

Bit 12

Select

Interrupt

Send

(BI)

(CTS)

Data Bit 5

Stick

Transmitter

Data

Bit 5

Bit 13

Parity

Holding

Set

Ready

(THRE)

(DSR)

Data Bit 6

Set

Transmitter

Ring

Bit 6

Bit 14

Break

Empty

Indicator

(TEMT)

(RI)

(Note 2)

Data Bit 7

Divisor

Data

Bit 7

Bit 15

Latch

Carrier

Access Bit

Detect

(DLAB)

(DCD)

Note 1

Bit 0 is the least significant bit It is the first bit serially transmitted or received

Note 2

When operating in the XT mode this bit will be set any time that the transmitter shift register is empty

Note 3

This bit no longer has a pin associated with it

Note 4

When operating in the XT mode this register is not available

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