PC87309VLJ datasheet(150/192 Pages) NSC

150 / 192 page

Enhanced Serial Port - UART1 (Logical Device 3)

150

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TABLE 6-13. Prescaler Select

Bit 6 - Reserved

Read/Write 0.

Bit 7 - Baud Divisor Register Lock (LOCK)

When set to 1, accesses to the Baud Generator Divisor

back are disabled from non-extended mode.

In this case two scratchpad registers overlaid with LB-

GD(L) and LBGD(H) are enabled, and any attempted

CPU access of the Baud Generator Divisor Register

through LBGD(L) and LBGD(H) will access the scratch-

pad registers instead. This bit must be set to 0 when ex-

tended mode is selected.

6.7.5

Reserved Register

Upon reset, all bits in Bank 2 register with offset 05h are set

to 0.

Bits 7-0 - Reserved

Read/write 0.

6.7.6

TX_FIFO Current Level Register (TXFLV)

This read-only register returns the number of bytes in the

TX_FIFO. It can be used to facilitate programmed I/O

modes during recovery from transmitter underrun in one of

the fast infrared modes.

Bits 4-0 - Number of Bytes in TX_FIFO (TFL(4-0))

These bits specify the number of bytes in the TX_FIFO.

Bits 7,6 - Reserved

Read/Write 0.

6.7.7

RX_FIFO Current Level Register (RXFLV)

This read-only register returns the number of bytes in the

RX_FIFO. It can be used for software debugging.

Bits 4-0 - Number of Bytes in RX_FIFO (RFL(4-0))

These bits specify the number of bytes in the RX_FIFO.

Bits 7,6 - Reserved

Read/Write 0.

Note: The contents of TXFLV and RXFLV are not frozen

during CPU reads. Therefore, invalid data could be re-

turned if the CPU reads these registers during normal

transmitter and receiver operation. To obtain correct da-

ta, the software should perform three consecutive reads

and then take the data from the second read, if first and

second read yield the same result, or from the third

read, if first and second read yield different results.

6.8

BANK 3 – MODULE REVISION ID AND SHADOW

REGISTERS

Bank 3 contains the Module Revision ID register which

identifies the revision of the module, shadow registers for

monitoring various registers whose contents are modified

by being read, and status and control registers for handling

the flow control.

TABLE 6-14. Bank 3 Register Set

Bit 5

Bit 4

Prescaler Value

1.625

Reserved

1.0

76543210

Reset

Required

Current Level

Bank 2,

TX_FIFO

TFL2

TFL4

TFL0

TFL1

TFL3

Extended Modes

Offset 06h

Reserved

Offset

Name

Description

00h

MRID

Module Revision ID Register

01h

SH_LCR

Shadow of LCR Register

(Read Only)

02h

SH_FCR

Shadow of FIFO Control Register

(Read Only)

03h

LCR/

BSR

Line Control Register/

Bank Select Register

04h-07h

Reserved

76543210

Reset

Required

Current Level

Bank 2,

RFL2

RFL4

RFL0

RFL1

RFL3

Extended Modes

Offset 07h

Reserved

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