PC87307 datasheet(48/218 Pages) NSC

48 / 218 page

Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)

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3.5.3

The KBC STATUS Register, Offset 64h,

Read Only

The STATUS register holds information regarding the sys-

tem interface status. Figure 3-9 shows the bit definition of

this register. This register is controlled by the KBC firmware

and hardware, and is read-only for the system.

FIGURE 3-9. KBC STATUS Register Bitmap

Bit 0 - OBF, Output Buffer Full

A 1 indicates that data has been written into the DB-

BOUT register by the KBC. It is cleared by a system

read operation from DBBOUT.

Bit 1 - IBF, Input Buffer Full

When a write operation is performed by the host system,

this bit is set to 1, which may be set up to trigger the IBF

interrupt. Upon executing an IN A, DBB instruction, it is

cleared.

Bit 2 - F0, General Purpose Flag

A general purpose flag that can be cleared or toggled by

the keyboard controller firmware.

Bit 3 - F1, Command/Data Flag

This flag holds the state of address line A2 while a write

operation is performed by the host system. It distin-

guishes between commands and data from the host

system. In this device, a write with A2 = 1 (hence F1 =

1) is defined as a command, and A2 = 0 (hence F1 = 0)

is data.

Bits 7-4, General Purpose Flags

These flags may be modified by KBC firmware.

3.6

INSTRUCTION TIMING

The KBC clock is first divided by 3 to generate the state tim-

ing, then by 5 to generate the instruction timing. Thus each

instruction cycle consists of five states and 15 clock cycles.

Most keyboard controller instructions require only one in-

struction cycle, while some require two cycles. Refer to the

8042 or PC87323VUL instruction set for details.

76543210

Reset

OBF Output Buffer Full

IBF Input Buffer Full

F0 General Purpose Flag

F1 Command or Data Flag

General Purpose

Flags

KBC Status Register

Offset 64h

Read Only

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