CDCV857B datasheet(6/16 Pages) TI1

6 / 16 page

CDCV857B, CDCV857BI

2.5-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 2010

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX UNIT

Without load

fO = 170 MHz

100

110

Without load

fO = 200 MHz

105

120

Differential outputs

i t d ith

fO = 170 MHz

200

240

IDD

Dynamic current on VDDQ

terminated with

120 Ω/CL = 0 pF

fO = 200 MHz

210

250

Differential outputs

i t d ith

fO = 170 MHz

260

300

terminated with

120 Ω/CL = 14 pF

fO = 200 MHz

280

320

ΔC

Part-to-part input capacitance

variation

VDDQ = 2.5 V, VI = VDDQ or GND

CI(Δ)

Input capacitance difference between

CLK and CLKB, FBIN, and FBINB

VDDQ = 2.5 V, VI = VDDQ or GND

0.25

Output capacitance

VDDQ = 2.5 V, VO = VDDQ or GND

2.5

3.5

† All typical values are at a respective nominal VDDQ.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature

MIN

MAX

UNIT

Operating clock frequency

200

MHz

fCLK

Application clock frequency

200

MHz

Input clock duty cycle

40%

60%

Stabilization time{ (PLL mode)

μs

Stabilization time} (Bypass mode)

† The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,

a fixed-frequency, fixed-phase reference signal must be present at CLK and VDD must be applied. Until phase lock is obtained, the specifications

for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply

for input modulation under SSC application.

‡ A recovery time is required when the device goes from power-down mode into bypass mode (AVDD at GND).

switching characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPLHw

Low to high level propagation delay time

Test mode/CLK to any output

3.5

tPHLw

High-to low level propagation delay time

Test mode/CLK to any output

3.5

Jitter (period) See Figure 7

66 MHz

−60

tjit(per)W

Jitter (period), See Figure 7

100/133/167/200 MHz

−35

Jitter (cycle to cycle) See Figure 4

66 MHz

−75

tjit(cc)W

Jitter (cycle-to-cycle), See Figure 4

100/133/167/200 MHz

−50

Half period jitter See Figure 8

66 MHz

−100

100

tjit(hper)W

Half-period jitter, See Figure 8

100/133/167/200 MHz

−75

tslr(o)

Output clock slew rate, See Figure 9

Load: 120 Ω/14 pF

V/ns

Static phase offset See Figure 5

66 MHz

–100

100

t(Ø)

Static phase offset, See Figure 5

100/133/167/200 MHz

–50

tsk(o)

Output skew, See Figure 6

Load: 120 Ω/14 pF

100

tr, tf

Output rise and fall times (20% − 80%)

Load: 120 Ω/14 pF

600

900

§ Refers to the transition of the noninverting output.

¶ This parameter is assured by design but can not be 100% production tested.

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