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PIC18F2331 bảng dữ liệu(PDF) 37 Page - Microchip Technology |
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PIC18F2331 bảng dữ liệu(HTML) 37 Page - Microchip Technology |
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37 / 396 page  2003 Microchip Technology Inc. Preliminary DS39616B-page 35 PIC18F2331/2431/4331/4431 3.3.1 PRI_IDLE MODE This mode is unique among the three low-power idle modes, in that it does not disable the primary system clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm up” or transition from another oscillator. PRI_IDLE mode is entered by setting the IDLEN bit, clearing the SCS bits, and executing a SLEEP instruc- tion. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified in Configuration Register 1H. The OSTS bit remains set in PRI_IDLE mode (see Figure 3-3). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of approximately 10 µs is required between the wake event and when code exe- cution starts. This is required to allow the CPU to become ready to execute instructions. After the wake- up, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-4). FIGURE 3-3: TRANSITION TIMING TO PRI_IDLE MODE FIGURE 3-4: TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE Q1 Peripheral Program PC PC + 2 OSC1 Q3 Q4 Q1 CPU Clock Clock Counter Q2 OSC1 Peripheral Program PC CPU Clock PC + 2 Q1 Q3 Q4 Clock Counter Q2 Wake Event CPU Start-up Delay |
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