NSC800D datasheet(51/76 Pages) NSC

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1211 Memory Block Moves and Searches (Continued)

76543210

11101101

10101001

Timing

M cycles

T states

16 (4 4 3 5)

Addressing Mode

REPEAT OPERATIONS

LDIR

Move data from memory location (HL) to memory location

(DE) increment memory pointers decrement byte counter

BC and repeat until BC e 0

(DE)

w (HL)

S NA

w DE a 1

Z NA

w HL a 1

H Reset

w BC b 1

PV Reset

Repeat until

N Reset

BC e 0

C NA

76543210

11101101

10110000

Timing

For BC i 0 M cycles

T states

21 (4 4 3 5 5)

For BCe0 M cycles

T states

16 (4 4 3 5)

Addressing Mode

(Note that each repeat is accomplished by a decrement of

the BC so that refresh etc continues for each cycle)

LDDR

Move data from memory location (HL) to memory location

(DE) decrement memory pointers and byte counter BC and

repeat until BC e 0

(DE)

w (HL)

S NA

w DE b 1

Z NA

w HL b 1

H Reset

w BC b 1

PV Reset

Repeat until

N Reset

BC e 0

C NA

76543210

11101101

10111000

Timing

For BC i 0 M cycles

T states

21 (4 4 3 5 5)

For BCe0 M cycles

T states

16 (4 4 3 5)

Addressing Mode

(Note that each repeat is accomplished by a decrement of

the BC so that refresh etc continues for each cycle)

CPIR

Compare data in memory location (HL) to the Accumulator

increment the memory decrement the byte counter BC and

repeat until BC e 0 or (HL) equals A

A b (HL)

S Set if sign of subtraction per-

formed for comparison is nega-

w HL a 1

tive

w BC b 1

Z Set if A e (HL) otherwise reset

Repeat until BC e 0

H Set according to borrow from

or A e (HL)

bit 4

PV Set if BC b 1 i 0 otherwise

reset

N Set

C NA

76543210

11101101

10110001

Timing

For BC i 0

M cycles

T states

21 (4 4 3 5 5)

For BC e 0

M cycles

T states

16 (4 4 3 5)

Addressing Mode

(Note that each repeat is accomplished by a decrement of

the PC so that refresh etc continues for each cycle)

CPDR

Compare data in memory location (HL) to the contents of

the Accumulator decrement the memory pointer and byte

counter BC and repeat until BC e 0 or until (HL) equals

the Accumulator

A b (HL)

S Set if sign of subtraction per-

formed for comparison is nega-

w HL b 1

tive

w BC b 1

Z Set according to equality of A

Repeat until BC e 0

and (HL) set if true

or A e (HL)

H Set according to borrow from

bit 4

PV Set if BC b 1 i 0 otherwise

reset

N Set

C NA

76543210

11101101

10111001

Timing

For BC i 0

M cycles

T states

21 (4 4 3 5 5)

For BC e 0

M cycles

T states

16 (4 4 3 5)

Addressing Mode

(Note that each repeat is accomplished by a decrement of

the BC so that refresh etc continues for each cycle)

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