ST25R3910 datasheet(22/65 Pages) STMICROELECTRONICS

22 / 65 page

Functional overview

ST25R3910

22/65

DocID029768 Rev 2

Direct Command Mode

Direct Command Mode has no arguments, so a single byte is sent. SPI operation mode bits

11 indicate Direct Command Mode. The following six bits define command code, sent MSB

to LSB. The command is executed on falling edge of last clock (see Figure 10).

Figure 10. SPI communication: direct command

Interrupt interface

When an interrupt condition is met the source of interrupt bit is set in the Interrupt Register

and the INTR pin transitions to high.

The microcontroller then reads the Interrupt Register to distinguish between different

interrupt sources. After the Interrupt Register is read its content is reset to 0 and INTR pin

signal transitions to low.

Note:

There may be more than one interrupt bit set in case the microcontroller does not

immediately read the Interrupt Register after the INTR signal has been set and another

event causing interrupt has occurred.

If an interrupt from a certain source is not required, it can be disabled by setting

corresponding bit in the Mask Interrupt Register. When masking a given interrupt source the

interrupt is not produced, but the source of interrupt bit is still set in Interrupt Register.

After reading the Interrupt Register the 13.56 MHz clock coming from the oscillator is used

to produce a reset signal that clears it and resets INTR signal. Practically in all interrupt

cases the oscillator is running when an interrupt is produced. The only exception is the

interrupt in the Initial NFC Target mode where only the Target Activation Detector is

operating. In this case the interrupt is cleared with first SCLK rising edge following reading

of the Interrupt Register (an extra dummy CLK pulse during reading of the Interrupt Register

or the first SCLK pulse of the next SPI command will do the job).

Table 3. INTR output

Name

Signal

Signal level

Description

INTR

Digital output

CMOS

Interrupt output pin

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