L5988D datasheet(19/52 Pages) STMICROELECTRONICS

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L5988D

Functional description

Considering ISS2/ISS1 = 22/5 = 4.4, the proper soft-start capacitor is simply calculated as

follows:

Equation 6

During the soft-start phase (VSS < 2.9 V):



the sink capability is always disabled (independently from the multifunction pin settings)

to be compatible with pre-biased output voltage



in case the overcurrent limit is detected, a constant current protection is provided in

order to deliver extra current for charging the output capacitor (see Section 5.5.2 for

description of current protection management).

During normal operation the CSS is discharged with a constant current of 22 A (typ.) only if:



HICCUP mode is triggered (see Section 5.5.2)



the input voltage goes below the UVLO threshold (see Section 5.5.3)



the internal temperature is over 150°C (see Section 5.5.4)

A new SS cycle will start when the VSS drops below the INH threshold.

New high performance ICs often require more than one supply voltage. Most of these

applications require well defined start-up sequencing, in order to avoid potential damage

and latch-up of the processing core. Sharing the same soft-start capacitor for a set of

regulators, the output voltages increase with the same slew rate implementing

a “simultaneous start-up” sequencing method.

5.5

Monitoring and protections

5.5.1

Overvoltage

The device provides the overvoltage protection monitoring the output voltage through the

FB pin. If the voltage sensed on FB pin reaches a value 20% (typ.) greater than the

reference of the error amplifier, the low-side MOSFET is turned on to discharge as fast as

possible the output capacitor. It is possible to set two different behaviors in case of OVP:



In case the OVP latched mode is active (see Section 5.1 on page 13), the internal

oscillator is suspended and the low side switch will be kept on until the input voltage

goes below the selected UVLO threshold or the SS/INH pin is forced below the INH

threshold.



In case of NOT latched OVP mode is active, the low side MOS is forced ON until the

feedback voltage is higher than the OVP threshold (20% greater than the reference of

the error amplifier).

CnF



Tss mS

 3.5



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